1. Field of the Invention
This invention relates to a magnetic memory device, a method for manufacturing such magnetic memory device, and an integrated circuit device using a plurality of such magnetic memory devices, and particularly to a magnetic memory device, a method for manufacturing such magnetic memory device, and an integrated circuit device using such magnetic memory devices, wherein the magnetic memory device is a nonvolatile magnetic memory device that memorizes information utilizing the change of resistance value depending on that the spin direction of a ferromagnetic material is parallel or anti-parallel.
2. Description of Related Art
Along with an extreme wide-spread of communication apparatuses and, in particular, personal digital assistants such as mobile terminals, higher performances such as high-integration, high-speed, low power consumption and the like are required to memory devices and logic devices that constitute these apparatuses. Particularly, the nonvolatile memory is thought to be an indispensable device in this ubiquitous age. In such a case of power shortage, trouble in power supply, or shutdown of a link between a server and a network by failure or something, the nonvolatile memory is able to protect important personal information. And those technologies relating to high density and large capacity have become important as a technology for replacing a hard disk and an optical disk which are basically impossible for miniaturization of apparatuses due to the existence of the movable parts.
Further, a recent mobile apparatus is designed to save power consumption as much as possible by employing a standby mode to an unnecessary circuit block, and accordingly, if a nonvolatile memory capable of combining a high-speed network memory and a large capacity storage memory is realized, it is possible to save power consumption and to delete unnecessary memory. Further, if such high speed and large capacity nonvolatile memory is realized, it becomes possible to carry out a so-called instant-on function which functions to start up immediately after the power is on.
As an nonvolatile memory, a flash memory using a semiconductor, a FRAM (Ferroelectric Random Access Memory) using a ferroelectric material and the like are now on the market, and active research and development for higher performances have been conducted. Recently, a magnetic memory called a MRAM (Magnetic Random Access Memory) or a MR (Magneto Resistance) memory utilizing a tunnel magneto-resistance effect has been manufactured by way of trial, and has gathered the attention as a new type of a nonvolatile memory employing a magnetic material. For example, please refer to a non-patent publication 1 (Peter K. Naji, Mark Durlam, Saied Tehrani, John Calder, Mark F. DeHerrera, “A 256 kb 3.0V 1T1MTJ Nonvolatile Magnetoresistive RAM”, 2001 IEEE International Solid-State Circuits Conference Digest of Technical Papers, (2001) p. 122–123). The MRAM is better than a flash memory in a random access operation, the number of rewritable operation, and a high speed operation, and is also better than FeRAM in the number of rewritable operation. In addition, both a high integration like DRAM and a high speed like SRAM are expected, so that the MRAM has a possibility of being replaced instead of an embedded memory for a system LDD.
The MRAM has a structure in which minute magnetic devices for recording information are regularly arranged, and a wiring operation is provided for accessing each of them. A general MRAM (Magnetic Random Access Memory) is now explained with reference to a conceptual perspective view which shows a main part in FIG. 7 with simplification. In FIG. 7, a portion of a read out circuit is omitted for simplification.
As shown in FIG. 7, a gate electrode (read word line) 26 is formed on a semiconductor substrate (p type semiconductor substrate, for example) 21 by way of a gate insulating film (not shown), and on the semiconductor substrate 21 of both sides of the gate electrode 26, diffusion layer areas (N+ diffusion layer area, for example) 27 and 28 are formed so as to configure a selecting field effect transistor 24. The above mentioned field effect transistor 24 functions as a switching element for read out operation. It is possible to use various switching elements such as diodes, bipolar transistors and the like in addition to n type or p type field effect transistors, in stead.
In the diffusion layer area 27 of the above mentioned field effect transistor 24, a contact (tungsten plug, for example, although not shown) is formed, and further, a sense line (not shown) to be connected to this contact is formed. In addition, in the diffusion layer area 28 of the above mentioned field effect transistor 24, a contact (tungsten plug, for example) 30 is formed.
One end of the lower electrode (bypass line) 17 is connected to the above mentioned contact 30, and the other end of the lower electrode 17 is connected to a storage cell (TMR device, for example) 13 having a magnetic tunnel junction (hereinafter referred to as MTJ). In addition, below the storage cell 13, a write word line 11 is formed by way of the lower electrode 17, and an insulating film (not shown). The above mentioned lower electrode 17 is made of a conductive material, and may be formed with a stacked structure of a conductive layer and an antiferromagnetic layer, or formed in a condition where a magnetic fixed layer is extensively formed.
The above mentioned storage cell 13 is formed on the above mentioned antiferromagnetic layer (not shown), and also above the above mentioned write word line 11, and is so configured as to sandwich a non-magnetic spacer layer (tunnel insulating layer) 303 between a ferromagnetic fixed layer 302 and a ferromagnetic free layer (storage layer) 304 in which a magnetization is easily rotatable. Further, a protecting layer (not shown) is formed on the storage cell 13.
In addition, a bit line 12 is formed to be connected to on a top surface of the above mentioned storage cell 13 and to be three-dimensionally intersecting (at right angle, for example) with the above mentioned write word line 11 while sandwiching the above mentioned storage cell 13.
In the magnetic memory device thus configured as above, the writing operation is carried out by controlling the direction of magnetization of the storage cell 13 based on a synthetic magnetic field caused by current flowing through both the write word line 11and the bit line 12. In the reading out operation, a cell selection is carried out by the field effect transistor 24, and the difference in the direction of magnetization is detected as a difference in a voltage signal based on the magnetoresistance effect of the storage cell 13. In this case, various transistors such as field effect transistors and diodes are able to be used as selecting devices for reading out operation.
Next, a MRAM cell array in which magnetic memory devices described in FIG. 7 are arranged with a certain regularity is described with reference to a conceptual circuit diagram shown in FIG. 8.
As shown in FIG. 8, the magnetic memory devices each having a configuration as described with reference to FIG. 7 are connected in a matrix form by a read word line 26, a write word line 11, and a bit line 12. Namely, in the storage cell 13 of each of the magnetic memory devices, the fixed layer side of the storage cell 13 is connected to one of diffusion layers of the field effect transistor 24 and the free layer side thereof is connected to the bit line 12. In addition, the other of the diffusion layers of the field effect transistor 24 is connected to ground, and the gate electrode of the field effect transistor 24 is connected to the read word line 26. Further, the write word line 11 is three dimensionally intersected (at right angle) with the bit line 12, and is provided beneath the fixed layer side of the storage cell 13.
In the MRAM as described above, its writing operation is carried out by controlling the direction of magnetization of the targeted storage cell 13 where the write word line 11 and the bit line 12 intersects to each other with a synthesized magnetic field caused by flowing current through both the write word line 11 and the bit line 12. A transistor is used for reading out operation of the stored information in the memory cell. That is, it is able to read out stored information of the targeted cell where the write word line 11 and the bit line 12 intersects to each other by setting the read word line 26 where the targeted cell is connected to be a high (on) level, and by detecting a voltage change of the bit line 12. In this case, a potential of the bit line 12 designates a value proportional to a magnetoresistance (ΔR) determined by the direction of magnetization of the storage cell 13.
In the cell having MTJ, the direction of magnetization of the ferromagnetic fixed layer is fixed by an antiferromagnetic layer. The writing operation is carried out by rotating the direction of magnetization of the ferromagnetic free layer with current magnetic field generated by a word line and a bit line. In the cell having MTJ, its magnetoresistance changes depending on an angle of magnetization by a ferromagnetic free layer and a ferromagnetic fixed layer. A value of the magnetoresistance becomes a maximum value when two directions of the magnetization of the ferromagnetic fixed layer and the ferromagnetic free layer are anti-parallel, and becomes a minimum value when these directions of the magnetization are parallel. In general, the distinction of the magnetizing condition as above is stored with reference to the information of [0] and the information of [1]. In case of the reading out operation, this distinction of the magnetoresistance value is detected as a distinction of a voltage signal.
In order to stably drive the MRAM depicted in FIG. 8, it is important to suppress variation in a switching magnetic field at each cell. This switching magnetic field depends on the coercive force (Hc) of the ferromagnetic free layer and the interlayer coupling magnetic field (Hf) acting between the ferromagnetic fixed layer and the ferromagnetic free layer. Regarding a method for reducing the variation of the interlayer coupling magnetic field (Hf) is already described in an patent application. For example, please refer to a Japanese patent application 2002-091259 (laid-opened as OP2002-091259). This laid-opened patent describes that a MTJ cell having better flatness is obtained by defining an average grain diameter (30 nm or less) of a crystal grain and a crystalline orientation (no orientation) of either antiferromagnetic layer or ferromagnetic fixed layer within the cell having MTJ, and as a result, it is possible to suppress the interlayer coupling magnetic field (Hf) between the ferromagnetic fixed layer and the ferromagnetic free layer to be small, and further, to suppress a distribution of the variation in the interlayer coupling magnetic field (Hf) at each cell. On the other hand, regarding the variation factor in the coercive force (Hc), it is pointed out a possibility of depending generally on a shape of the cell having MTJ. For example, please refer to a non-patent publication 2 (Ricardo C. Sousa and Paulo P. Freitas, “Dynamic Switching of Tunnel Junction MRAM Cell with Nanosecond Field Pulses”, IEEE Transactions, (2000) Vol.36, No.5, p. 2770–2772. However, in case of fabricating an actual MRAM device, even though shapes of the cells having MTJs are arranged to be almost the same, variation in the coercive force (Hc) is still observed, and accordingly, it is suggested that there is a possibility of another factor.
Conventionally, in a MTJ cell having an antiferromagnetic layer, a ferromagnetic fixed layer, a non-magnetic spacer layer, and a ferromagnetic free layer, the reason for causing the variation in a coercive force (Hc) of the ferromagnetic free layer has not been fully cleared.